It is an ongoing concern in modern communication systems, in particular in wireless communication systems, to provide low power consumption and to lower the analogue area. Therefore, the polar architecture can be used for implementing the transmitter.
Furthermore, it is desired to implement such a polar transmitter in a predominant manner digitally. An example of a digital polar transmitter according to prior art is shown in FIG. 1. As can be seen from FIG. 1, a phase component 2 and an envelope component 4 are the two data input signals. For instance, these signals 2 and 4 can be generated by a digital signal processor (DSP) or the like.
The envelope component 4 can be added to the signal to be amplified via the voltage supply of a provided power amplifier 10. Subsequently, a band pass filter 12 can be arranged, which comprises an output terminal 14. This output terminal 14 can be connected to suitable sending means, like an antenna (not shown).
The phase component 2 can be generated by modulating the digital phase locked loop (ADPLL). An ADPLL may encompass generally as main blocks a digitally controlled oscillator (DCO) 8 and a phase to frequency (PF) converter 6. Thereby, the time-to-digital converter may have a high speed accumulator, such as an integer converter counting the full cycles of the DCO, and a fractional converter (TDC) for measuring the fractional phase error compared to the DCO cycle.
From document US 2007/0085579 a two point modulation of the ADPLL is known. In particular, frequency samples can be applied to the ADPLL in a two point way, using a reference frequency as the sampling rate. Such a polar transmitter can be used for applications comprising a low symbol period, since in these cases the ADPLL provides enough oversampling to satisfy the Nyquist criterion for representing the modulated signal in the time discrete domain.
For other application with higher symbol rates, like wideband orthogonal frequency division multiplex (OFDM), a sampling rate higher then the usually used reference frequency is needed. The only suitable clocks with such high frequencies are provided at the output of the accumulator clocked by the DCO. A problem arises by using the DCO, since the clock has a data dependent jitter as the DCO is modulated during transition. Furthermore, since the phase is created by integrating the frequency samples, the phase error will be accumulated.
FIG. 2 shows an exemplified diagram of OFDM phase signals. The reference sign 16 indicates unwrapped phase, while reference sign 18 indicates the time axis, for instance, in μs. Furthermore, the curve 20 represents the ideal phase and the dotted curve 22 represents the phase at the output of the DCO. From this diagram, an accumulation of the phase error can easily be seen. Such an accumulation of the phase error can deteriorate the error vector magnitude (EVM) at the output of the polar transmitter.
Therefore, it is an object of the present application to provide a polar transmitter comprising at least a reduced phase error. A further object is to prevent a phase error accumulation due to modulation induced clock jitter. Another object is to improve the EVM at the output of the polar transmitter.